Data Value Compare (Dvc) Debug Event - IBM PPC440X5 CPU Core User Manual

Preliminary
dcbst, dcbf
dcbst and dcbf instructions are considered "loads" with respect to storage access control,
The
since they do not change the contents of a given storage location. They may merely cause the
data at that storage location to be moved from the data cache out to memory. However, in a
debug environment, the fact that these instructions may lead to write operations on the external
interface is typically the event of interest. Therefore, these instructions are considered "stores"
with respect to DAC debug events, and may cause DAC write debug events.
dcbt, dcbtst, icbt
The touch instructions are considered "loads" with respect to both storage access control
and DAC debug events. However, these instructions are treated as no-ops if they reference
caching inhibited storage locations, or if they cause Data Storage or Data TLB Miss
exceptions. Consequently, if a touch instruction is being treated as a no-op for one of these
reasons, then it does not cause a DAC read debug event. However, if a touch instruction is
not being treated as a no-op for one of these reasons, it may cause a DAC read debug
event.
dcba
The dcba instruction is treated as a no-op by the PPC440x5, and thus will not cause a DAC
debug event.
icbi
The icbi instruction is considered a "load" with respect to both storage access control and DAC
debug events, and thus may cause a DAC read debug event.
dccci, dcread, iccci, icread
The dccci and iccci instructions do not generate an address, but rather they affect the entire
data and instruction cache, respectively. Similarly, the dcread and icread instructions do not
generate an address, but rather an "index" which is used to select a particular location in the
respective cache, without regard to the storage address represented by that location.
Therefore, none of these instructions cause DAC debug events.
stwcx.
If the execution of a stwcx. instruction would otherwise have caused a DAC write debug event,
but the processor does not have the reservation from a lwarx instruction, then the DAC write
debug event does not occur since the storage location does not get written.
lswx, stswx
DAC debug events do not occur for lswx or stswx instructions with a length of 0
(XER[TBC] = 0), since these instructions do not actually access storage.

8.3.3 Data Value Compare (DVC) Debug Event

DVC debug events occur when execution is attempted of a load, store, or dcbz instruction for which the data
storage address and other parameters match the DAC conditions specified by DBCR0, DBCR2, and the DAC
registers, and for which the data accessed matches the DVC conditions specified by DBCR2 and the DVC
registers. In other words, in order for a DVC debug event to occur, the conditions for a DAC debug event must
first be met, and then the data must also match the DVC conditions. Data Address Compare (DAC) Debug
debug.fm.
September 12, 2002
User's Manual
PPC440x5 CPU Core
Page 231 of 589