Avaya S8700 Maintenance Manual page 353

SYNC (Port-Network Synchronization)
5. Execute the disable synchronization-switch and then the enable
6. Check the Error Log and execute the status synchronization
7. For duplicated Tone-Clock circuit packs in the master port network:
b. This error indicates that Synchronization Maintenance has been disabled
via the disable synchronization-switch command. Execute the enable
synchronization-switch command to enable Synchronization
Maintenance reference switching and to resolve this alarm.
c. This error indicates a problem with the secondary DS1 reference. It will be
cleared when the secondary reference is restored. Refer to note (a) to
resolve this error substituting secondary for primary in the preceding
resolution steps.
d. This error indicates that the Tone-Clock circuit pack is providing the timing
source for the system. The primary and secondary (if administered) are
not providing a valid timing signal. Investigate errors 1 and 257 to resolve
this error.
e. This error indicates excessive switching of system synchronization
references has occurred. When this error occurs, synchronization is
disabled and the Tone-Clock circuit pack (in the master port network)
becomes the synchronization reference for the system. Execute the
following steps to resolve this error:
1. Check for timing loops, and resolve any loops that exist.
2. Test the active Tone-Clock circuit pack in the master port network
555-233-142
synchronization-switch commands. These two commands (when
executed together) will switch the system synchronization reference
to the primary DS1 Interface circuit pack.
cab # command to verify that the primary DS1 Interface circuit pack
is still the system synchronization reference.
If the primary DS1 Interface circuit pack is not the system
synchronization reference and the master port network does not
have duplicate Tone-Clock circuit packs, escalate the problem.
Otherwise, continue with the following step.
Enter set tone-clock UUC to interchange Tone-Clocks in the
master port network, and repeat the disable/enable commands
described in the previous step.
via the test Tone-Clock UUC long command.
Check the Error Log for TDM-CLK errors, and verify that TDM bus
Clock Circuit Status Inquiry test (#148) passes.
If Test #148 fails with Error Code 2–32, see
Clock)'' to resolve the problem. If not, continue with the following
steps.
''TDM-CLK (TDM Bus
Issue 1 May 2002 8-1049