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Pad Module Configuration Register (PDMCR2)
Table 2-5. PDMCR Field Descriptions (continued)
Bits
Name
7
SPRDS
Disables weak pull-up/pull down devices enabled at the assertion of PORESET/TRST or HRESET.
Signals affected by the SPRDS bit include the following: BDIP, TA, TS, TEA, RD/WR, BR, BG, BB,
TSIZ, BI/STS, BURST.
0 Enable weak pull-up/pull down devices on pads controlled by this signal.
1 Disable weak pull-up/pull down devices on pads controlled by this signal.
8
--
Reserved.
9:14
PULL_DIS Disables weak pull up-or-down devices enabled at the assertion of PORESET/TRST or HRESET.
Signals affected by these bits include the following:
0 Enable weak pull-up/pull-down devices on pads controlled by this signal.
1 Disable weak pull-up/pull-down devices on pads controlled by this signal.
2.4
Pad Module Configuration Register (PDMCR2)
The PDMCR2 controls alternate functionality of signals shared between different modules,
as well as the pre-discharge circuitry to allow 5V friendliness on the data bus.
MSB
0
HRESET
16
HRESET
Addr
Figure 2-3. Pads Module Configuration Register 2 (PDMCR2)
PCS_IN[3:0] are driven from the QSMCM module.
PCS_OUT[7:0] values are driven by the corresponding
PCS[7:0] pads. If all of the PCS enable bits PCS4EN,
PCS5EN, PCS6EN and PCS7EN bits are zero, PCS[3:0] will
be driven directly by the QSMCM module. If one or more of
these enable bits is set, the enhanced PCS function is selected,
and the enabled pads drive PCS_OUT[7:0] value, as shown in
Table 25-10.
2.5
MPC533 Development Support Signal Sharing
On the MPC533, the JTAG, BDM, and READI (Nexus interface) signals are all shared.
Only one set of signals can be active at a time. Table 2-6 shows the shared functions in the
different modes.
2-24
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1
2
3
4
5
0000_0000_0000_0000
17
18
19
20
21
0000_0000_0000_0000
MPC533 Reference Manual
Description
6
7
8
9
22
23
24
25
0x2F C038
NOTE
10
11
12
13
14
26
27
28
29
30
MOTOROLA
15
LSB
31
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