Motorola MPC533 Reference Manual page 880

Program Flow Tracking
3. Issue decoded instructions at the top of the prefetch queue to the execution units,
and load processor status into history buffer [six instructions deep].
4. If the conditional branch instruction which was predicted taken, is subsequently
discovered to be mispredicted (condition not met), fetched instructions (from the
new target address specified by the branch instruction) are flushed. The cancelled
branch and the number of flushed instructions are signalled through the VF signals.
Now fetching of instructions is started from the old address (before the branch was
predicted as taken).
5. An instruction is 'retired' when the execution unit completes execution (without an
exception) of the issued instruction (write-back completed) and the instruction is at
the top of the history buffer queue; (i.e., all previously issued instructions
completed without exception).
— Issued instructions may complete execution out of order, but are always retired
from the history buffer in order.
6. When an instruction-caused exception is recognized, instructions that appear earlier
in the instruction stream are required to complete before the exception is taken. An
instruction is said to have "completed" when the results of that instruction's
execution has been committed to the appropriate registers (i.e., following the
writeback stage).
— Exception conditions may be recognized out of order, but they are handled
strictly in order.
7. Instructions that appear after the exception-causing instruction which have not been
executed are flushed from the prefetch queue. The number of instructions flushed is
signalled via the VF signals. Instructions that appear after the exception-causing
instruction which have been executed are flushed from the history buffer. The
number of instructions flushed from the history buffer are signaled via the VFLS
signals.
8. When exceptions occur, information about the state of the processor is saved to
certain registers, and the processor begins execution at an address predetermined
for each exception.
As can be seen from the above flow, the following issues arise, when tracking the execution
of the RCPU:
1. Not all fetched (decoded) instructions are executed.
2. Not all executed (issued and completed) instructions are retired.
3. Taken branches may be cancelled due to misprediction or exceptions.
4. Executed instructions (sequential or branches) which are subsequent to the
exception-causing instruction will be flushed from the history buffer due to
exception.
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