Motorola MPC533 Reference Manual page 11

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8.7.2 Power Mode Descriptions.............................................................................. 8-17
8.7.3 Exiting from Low-Power Modes ................................................................... 8-18
8.7.3.1 Exiting from Normal-Low Mode............................................................... 8-19
8.7.3.2 Exiting From Doze Mode .......................................................................... 8-19
8.7.3.3 Exiting From Deep-Sleep Mode................................................................ 8-19
8.7.3.4 Exiting from Power-Down Mode .............................................................. 8-20
8.7.3.5 Low-Power Modes Flow ........................................................................... 8-20
8.8 Basic Power Structure........................................................................................ 8-22
8.8.1 General Power Supply Definitions ................................................................ 8-22
8.8.2 Chip Power Structure..................................................................................... 8-22
8.8.2.1 NVDDL ..................................................................................................... 8-22
8.8.2.2 QVDDL ..................................................................................................... 8-22
8.8.2.3 VDD........................................................................................................... 8-23
8.8.2.4 VDDSYN, VSSSYN ................................................................................. 8-23
8.8.2.5 KAPWR..................................................................................................... 8-23
8.8.2.6 VDDA, VSSA............................................................................................ 8-23
8.8.2.7 VFLASH.................................................................................................... 8-23
8.8.2.8 VDDF, VSSF ............................................................................................. 8-23
8.8.2.9 VDDH........................................................................................................ 8-23
8.8.2.10 VSS ............................................................................................................ 8-23
8.8.3 Keep-Alive Power.......................................................................................... 8-24
8.8.3.1 Keep-Alive Power Configuration .............................................................. 8-24
8.8.3.2 Keep-Alive Power Registers Lock Mechanism......................................... 8-24
8.9 Supply Failure Detection .................................................................................. 8-26
8.10 Power-Up/Down Sequencing............................................................................. 8-27
8.11 Clocks Unit Programming Model...................................................................... 8-29
8.11.1 System Clock Control Register (SCCR)........................................................ 8-29
8.11.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) ........................... 8-33
8.11.3 Change of Lock Interrupt Register (COLIR)................................................. 8-36
8.11.4 Control Register (VSRMCR) ....................................................................... 8-37
9.1 Features ................................................................................................................ 9-1
9.2 Bus Transfer Signals ............................................................................................ 9-1
9.3 Bus Control Signals ............................................................................................. 9-2
9.4 Bus Interface Signal Descriptions........................................................................ 9-4
9.5 Bus Operations..................................................................................................... 9-8
9.5.1 Basic Transfer Protocol.................................................................................... 9-8
9.5.2 Single Beat Transfer ........................................................................................ 9-9
9.5.2.1 Single Beat Read Flow ................................................................................ 9-9
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Contents
Title
Chapter 9
External Bus Interface
Contents
Page
Number
xi