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. .
AN44
.
AN59
V
RH
V
RL
Figure 13-18. QADC64E Analog Subsystem Block Diagram
13.4.1.1 Conversion Cycle Times
Total conversion time is made up of initial sample time, final sample time, and resolution
time. Initial sample time refers to the time during which the selected input channel is
coupled through the buffer amplifier to the sample capacitor. This buffer is used to quickly
reproduce its input signal on the sample capacitor and minimize charge sharing errors.
During the final sampling period the amplifier is bypassed, and the multiplexer input
charges the sample capacitor array directly for improved accuracy. During the resolution
period, the voltage in the sample capacitor is converted to a digital value and stored in the
SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 6, 8, or 16
QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is ten
QCLK cycles.
Therefore, conversion time requires a minimum of 14 QCLK clocks (seven µs with a
2.0-MHz QCLK). If the maximum final sample time period of 16 QCLKs is selected, the
total conversion time is 28 QCLKs or 14 µs (with a 2.0-MHz QCLK)
Figure 13-19 illustrates the timing for conversions.
MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
+
Buffer
AMP
-
Decoder
Sample
6
RDAC
(7 BIT)
CHAN
IST
State Mach, SAR and SAR Buffer
REF
CCW Buffer
Result
10
Data Bus
STOP
Final
Sample
CAP Array
Equals CDAC
Buffer
CONV.
CDAC
(4 BIT)
CRH
CRL
7
4 (one is offset)
WCCW EOS/EOC
Standard Converter Interface
Analog Subsystem
BIAS
2
-
COMP.
+
Zero
CLK
13-33
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