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User Instruction Set Architecture (UISA) Register Set
• A specified field of the CR can be set by an instruction (mcrxr) to move to the CR
from the XER.
• Condition register logical instructions can be used to perform logical operations on
specified bits in the condition register.
• CR0 can be the implicit result of an integer operation.
• A specified CR field can be the explicit result of an integer compare instruction.
Instructions are provided to test individual CR bits.
3.7.4.1
Condition Register CR0 Field Definition
In most integer instructions, when the CR is set to reflect the result of the operation (that is,
when Rc = 1), and for addic., andi., and andis., the first three bits of CR0 are set by an
algebraic comparison of the result to zero; the fourth bit of CR0 is copied from XER[SO].
For integer instructions, CR[0:3] are set to reflect the result as a signed quantity. The EQ
bit reflects the result as an unsigned quantity or bit string.
The CR0 bits are interpreted as shown in Table 3-7. If any portion of the result (the 32-bit
value placed into the destination register) is undefined, the value placed in the first three
bits of CR0 is undefined.
CR0 Bit
0
Negative (LT). This bit is set when the result is negative.
1
Positive (GT). This bit is set when the result is positive (and not zero).
2
Zero (EQ). This bit is set when the result is zero.
3
Summary overflow (SO). This is a copy of the final state of XER[SO] at the completion of the instruction.
3.7.4.2
Condition Register CR1 Field Definition
In all floating-point instructions when the CR is set to reflect the result of the operation (that
is, when Rc = 1), the CR1 field (bits 4 to 7 of the CR) is copied from FPSCR[0:3] to indicate
the floating-point exception status. For more information about the FPSCR, see
Section 3.7.3, "Floating-Point Status and Control Register (FPSCR)." The bit settings for
the CR1 field are shown in Table 3-8.
CR1 Bit
0
Floating-point exception (FX). This is a copy of the final state of FPSCR[FX] at the completion of the
instruction.
1
Floating-point enabled exception (FEX).This is a copy of the final state of FPSCR[FEX] at the completion of
the instruction.
3-18
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 3-7. Bit Settings for CR0 Field of CR
Table 3-8. Bit Settings for CR1 Field of CR
MPC533 Reference Manual
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