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These signals are used to generate the "equal and less than" signals according to the
compare size programmed (byte, half-word, word). When operating in byte mode all
signals are significant, when operating in half-word mode only four signals from each 32
bit comparator are significant. When operating in word mode only two signals from each
32 bit comparator are significant.
From the new "equal and less than" signals and according to the compare type programmed
one of the following four match events are generated: equal, not equal, greater than, less
than. Therefore, from the two 32-bit comparators eight match indications are generated:
Gmatch[0:3], Hmatch[0:3].
According to the lower bits of the address and the size of the cycle, only match indications
that were detected on bytes that have valid information are validated, the rest are negated.
Note that if the cycle executed has a smaller size than the compare size (e.g., a byte access
when the compare size is word or half-word) no match indication will be asserted.
Using the match indication signals four load/store data events are generated in the
following way.
Event Name
G
(Gmatch0 | Gmatch1 | Gmatch2 | Gmatch3)
H
(Hmatch0 | Hmatch1 | Hmatch2 | Hmatch3)
(G&H)
((Gmatch0 & Hmatch0) | (Gmatch1 & Hmatch1) | (Gmatch2 & Hmatch2) | (Gmatch3 & Hmatch3))
(G | H)
((Gmatch0 | Hmatch0) | (Gmatch1 | Hmatch1) | (Gmatch2 | Hmatch2) | (Gmatch3 | Hmatch3))
1
'&' denotes a logical AND, '|' denotes a logical OR
The four load/store data events together with the match events of the load/store address
comparators and the instruction watchpoints are used to generate the load/store watchpoints
and breakpoint according to the programming.
Table 21-11. Load/Store Watchpoints Programming Options
Name
Description
LWP0
First
Load/store
watchpoint
LWP1
Second
Load/store
watchpoint
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 21-10. Load/Store Data Events
Event Function
Instruction Events
Programming
Options
IWP0, IWP1, IWP2,
IWP3,
ignore instruction
events
IWP0, IWP1, IWP2,
IWP3,
ignore instruction
events
Chapter 21. Development Support
Watchpoints and Breakpoints Support
1
L-address Events
Programming Options
Comparator E
Comparator F
Comparators (E&F)
Comparators (E | F)
ignore L-addr events
Comparator E
Comparator F
Comparators (E&F)
Comparators (E | F)
ignore I-addr events
L-data Events
Programming Options
Comparator G
Comparator H
Comparators (G&H)
Comparators (G | H)
ignore L-data events
Comparator G
Comparator H
Comparators (G&H)
Comparators (G | H)
ignore L-data events
21-23
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