Motorola MPC533 Reference Manual page 411

Bits Name
0:16 BA Base address. These bits are compared to the corresponding unmasked address signals among
ADDR[0:16] to determine if a memory bank controlled by the memory controller is being accessed
by an internal bus master. (The address types are also compared.) These bits are used in
conjunction with the AM[0:16] bits in the OR.
17:19 AT Address type. This field can be used to require accesses of the memory bank to be limited to a
certain address space type. These bits are used in conjunction with the ATM bits in the OR. Note
that the address type field uses only AT[0:2] and does not need AT[3] to define the memory type
space. For a full definition of address types, refer to Section 9.5.8.6, "Address Types".
20:21 PS Port size
00 32-bit port
01 8-bit port
10 16-bit port
11 Reserved
1
22 SST Short Setup Time – This field specifies the setup time required for this memory region.
0 Normal setup time (like the MPC555)
1 Short Setup Time selected
Note that an external burst access with short setup timing will corrupt any USIU register load/store
if SCCR[EBDF] is not 0b00. Refer to Table 8-9.
23 WP Write protect. An attempt to write to the range of addresses specified in a base address register
that has this bit set can cause the TEA signal to be asserted by the bus-monitor logic (if enabled),
causing termination of this cycle.
0 Both read and write accesses are allowed
1 Only read accesses are allowed. The CSx signal and TA are not asserted by the memory
controller on write cycles to this memory bank. WPER is set in the MSTAT register if a write to
this memory bank is attempted
24 — Reserved
25 BL Burst Length – This field specifies the maximum number of words that may comprise a burst
access for this memory region. This field has an effect only in the case when the burst accesses
are initiated by the USIU (SIUMCR[BURST_EN] =1).
0 Burst access of up to 4 words
1 Burst access of up to 8 words
26 WEBS Write-enable/byte-select. This bit controls the functionality of the WE/BE pads.
0 The WE/BE pads operate as WE
1 The WE/BE pads operate as BE
27 TBDIP Toggle-burst data in progress. TBDIP determines how long the BDIP strobe will be asserted for
each data beat in the burst cycles.
28 LBDIP Late-burst-data-in-progress (LBDIP). This bit determines the timing of the first assertion of the
BDIP signal in burst cycles.
NOTE: Do not set both LBDIP and TBDIP bits in a region's base registers; behavior in such cases
is unpredictable.
0 Normal timing for BDIP assertion (asserts one clock after negation of TS)
1 Late timing for BDIP assertion (asserts after the programmed number of wait states)
29 SETA External transfer acknowledge
0 TA generated internally by memory controller
1 TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may
have no meaning when this bit is set
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 10-9. BR0–BR3 Bit Descriptions
Chapter 10. Memory Controller
Description
Programming Model
10-35