Motorola MPC533 Reference Manual page 330

Bus Operations
CLKOUT
BR
BG
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
Data
TA
Figure 9-9. Single Beat Basic Write Cycle Timing – One Wait State
9.5.2.3 Single Beat Flow with Small Port Size
The general case of single beat transfers assumes that the external memory has a 32-bit port
size. The MPC533 provides an effective mechanism for interfacing with 16-bit and 8-bit
port size memories, allowing transfers to these devices when they are controlled by the
internal memory controller.
In this case, the MPC533 attempts to initiate a transfer as in the normal case. If the bus
interface receives a small port size (16 or 8 bits) indication before the transfer acknowledge
to the first beat (through the internal memory controller), the MCU initiates successive
transactions until the completion of the data transfer. Note that all the transactions initiated
to complete the data transfer are considered to be part of an atomic transaction, so the MCU
9-14
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Receive bus grant and bus busy negated
O
O
Assert BB, drive address and assert TS
O
O
Wait state
MPC533 Reference Manual
O
Data is sampled
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