Motorola MPC533 Reference Manual page 431

11.8.2 Transaction Size
All L2U registers are defined by MPC500 architecture as being 32-bit registers in normal
mode. There is no MPC500 instruction to access either a half word or a byte of the special
purpose register.
All L2U registers are only word accessible (read and write) in peripheral mode. A
half-word or byte access in peripheral mode will result in a word transaction.
11.8.3 L2U Module Configuration Register (L2U_MCR)
The L2U module configuration register (L2U_MCR) is used to control the L2U module
operation.
MSB 1 2
0
Field SP LSHOW
Reset
16 17 18
Field
Reset
Addr
Figure 11-4. — L2U Module Configuration Register (L2U_MCR)
Bits Name
0 SP CALRAM Protection (SP) bit is used to protect the CALRAM on the L-bus from U-bus accesses.
Any attempt to set or clear the SP bit from the U-bus side has no affect.
Once this bit is set, the L2U blocks all CALRAM accesses initiated by the U-bus masters and the
access is terminated with a data error on the U-bus.
If L-bus show cycles are enabled, setting this bit will disable L-bus CALRAM show cycles.
1:2 LSHOW LSHOW bits are used to configure the show cycle mode for cycles accessing the L-bus slave e.g.
CALRAM
00 Disable show cycles
01 Show address and data of all L-bus space write cycles
10 Reserved
11 Show address and data of all L-bus space read and write cycles
3:31 — Reserved
11.8.4 Region Base Address Registers (L2U_RBAx)
The L2U region base address register (L2U_RBAx) defines the base address of a specific
region protected by the data memory protection unit. There are four registers (x = 0...3),
one for each supported region.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3 4 5 6
0000_0000_0000_0000
19 20 21 22
0000_0000_0000_0000
Table 11-7. L2U_MCR Bit Descriptions
Chapter 11. L-Bus to U-Bus Interface (L2U)
7 8 9 10
—
23 24 25 26
—
SPR 568
Description
L2U Programming Model
11 12 13 14
27 28 29 30
11-15
15
LSB
31