Motorola MPC533 Reference Manual page 903

debug enable register (DER) is set, the CPU enters debug mode rather then the check stop
state.
The different actions taken by the CPU when a machine check interrupt is detected are
shown in the following table.
Table 21-12. Check Stop State and Debug Mode
Debug
MSR Mode
ME
Enable
0 0
1 0
0 1
0 1
1 1
1 1
1
Check stop enable bit in the debug enable register (DER)
2
Machine check interrupt enable bit in the debug enable register (DER)
21.3.1.4 Saving Machine State upon Entering Debug Mode
If entering debug mode was as a result of any load/store type exception, and therefore the
DAR (data address register) and DSISR (data storage interrupt status register) have some
significant value, these two registers must be saved before any other operation is
performed. Failing to save these registers may result in loss of their value in case of another
load/store type exception inside the development software.
Since exceptions are treated differently when in debug mode (refer to Section 21.3.1.5,
"Running in Debug Mode"), there is no need to save machine status save/restore zero
register (SRR0) and machine status save/restore one register (SRR1).
21.3.1.5 Running in Debug Mode
When running in debug mode all fetch cycles access the development port regardless of the
actual address of the cycle. All load/store cycles access the real memory system according
to the cycle's address. The data register of the development port is mapped as a special
control register therefore it is accessed using mtspr and mfspr instructions via special
load/store cycles (refer to Section 21.6.13, "Development Port Data Register (DPDR)").
Exceptions are treated differently when running in debug mode. When already in debug
mode, upon recognition of an exception, the exception cause register (ECR) is updated
according to the event that caused the exception, a special error indication (ecr_or) is
asserted for one clock cycle to report to the development port that an exception occurred
and execution continues in debug mode without any change in SRR0 and SRR1. ECR_OR
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1 2
CHSTPE MCIE
X X
X X
0 X
1 X
X 0
X 1
Chapter 21. Development Support
Development System Interface
Action Performed by the CPU when
Detecting a Machine Check Interrupt
Enter the check stop state
Branch to the machine check interrupt
Enter the check stop state
Enter Debug Mode
Branch to the machine check interrupt
Enter Debug Mode
Exception Cause
Register (ECR)
Value
0x2000_0000
0x1000_0000
0x2000_0000
0x2000_0000
0x1000_0000
0x1000_0000
21-33