Motorola MPC533 Reference Manual page 284

System Clock During PLL Loss of Lock
OSCCLK
Division Factor
DIVF[0:4]
Feedback
8.2.5 PLL Pins
The following pins are dedicated to the PLL operation:
• VDDSYN — Drain voltage. This is the V
The voltage should be well-regulated and the pin should be provided with an
extremely low impedance path to the V
to VSSSYN by a 0.1 µF capacitor located as close as possible to the chip package.
• VSSSYN — Source voltage. This is the V
The pin should be provided with an extremely low impedance path to ground.
VSSSYN should be bypassed to VDDSYN by a 0.1 µF capacitor located as close as
possible to the chip package.
• XFC — External filter capacitor. XFC connects to the off-chip capacitor for the PLL
filter. One terminal of the capacitor is connected to XFC, and the other terminal is
connected to VDDSYN.
— The off-chip capacitor must have the following values:
– 0 < MF + 1 < 4
– MF + 1 ≥ 4
Where MF = the value stored on MF[0:11]. This is one less
than the desired frequency multiplication.
8.3 System Clock During PLL Loss of Lock
At reset, until the SPLL is locked, the SPLL output clock is disabled.
During normal operation (once the PLL has locked), either the oscillator or an external
clock source is generating the system clock. In this case, if loss of lock is detected and the
LOLRE (loss of lock reset enable) bit in the PLPRCR is cleared, the system clock source
continues to function as the PLL's output clock. The USIU timers can operate with the input
8-6
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Up
Phase
Down
Comparator
Clock
Delay
Figure 8-3. System PLL Block Diagram
(1130 (MF + 1) – 80) pF
x
2100 (MF + 1) pF
x
MPC533 Reference Manual
XFC
Charge
Pump
VDDSYN / VSSSYN
Multiplication Factor
MF[0:11]
dedicated to the analog PLL circuits.
DD
power rail. VDDSYN should be bypassed
DD
dedicated to the analog PLL circuits.
SS
VCOOUT
VCO
MOTOROLA