Motorola MPC533 Reference Manual page 590

Trigger and Queue Interaction Examples
Recall QS = 0 => Queues disabled; QS = 8 => Q1 active, Q2 disabled; QS= 4 => Q1
paused, Q2 disabled.
A time separator was provided between the triggers and end of conversion (EOC). The
relationship to QCLK displayed is not guaranteed.
CWPQ1 or CWPQ2 typically lag CWP and only match CWP when the associated queue is
inactive. Another way to view CWPQ1(2) is that these registers update when EOC triggers
the result register to be written.
When the pause bit is set (CCW0), please note that CWP does not increment until triggered.
When the pause is not set (CCW1), the CWP increments with EOC.
The conversion results Q1 RES(x) show the result associated with CCW(x). So that R0
represents the result associated with CCW0.
Example 2 below shows the timing for conversions in gated mode single-scan with the
same assumptions as example 1 except:
• No pause bits set in any CCW
• External trigger gated single-scan mode for Q1
• Single-scan bit is set
When the gate closes and opens again the conversions start with the first CCW in Q1.
When the gate closes the active conversion completes before the queue goes idle.
When Q1 completes both the CF1 bit sets and the SSE bit clears.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual MOTOROLA