Motorola MPC533 Reference Manual page 282

System PLL
The PLL can perform the following functions:
• Frequency multiplication
• Skew elimination
• Frequency division
8.2.1 Frequency Multiplication
The PLL can multiply the input frequency by any integer between one and 4096. The
multiplication factor depends on the value of the MF[0:11] bits in the PLPRCR register.
While any integer value from one to 4096 can be programmed, the resulting VCO output
frequency must be at least 15 MHz. The multiplication factor is set to a predetermined value
during power-on reset as defined in Table 8-1.
8.2.2 Skew Elimination
The PLL is capable of eliminating the skew between the external clock entering the chip
(EXTCLK) and both the internal clock phases and the CLKOUT pin, making it useful for
tight synchronous timings. Skew elimination is active only when the PLL is enabled and
programmed with a multiplication factor of one or two (MF = 0 or 1). The timing reference
to the system PLL is the external clock input (EXTCLK pin).
8.2.3 Pre-Divider
A pre-divider before the phase comparator enables additional system clock resolution when
the crystal oscillator frequency is 20 MHz. The division factor is determined by the
DIVF[0:4] bits in the PLPRCR.
8.2.4 PLL Block Diagram
As shown in Figure 8-3, the reference signal, OSCCLK, goes to the phase comparator. The
phase comparator controls the direction (up or down) that the charge pump drives the
voltage across the external filter capacitor (XFC). The direction depends on whether the
feedback signal phase lags or leads the reference signal. The output of the charge pump
drives the VCO. The output frequency of the VCO is divided down and fed back to the
phase comparator for comparison with the reference signal, OSCCLK. The MF values, zero
to 4095, are mapped to multiplication factors of one to 4096. Note that when the PLL is
operating in 1:1 mode (refer to Table 8-1), the multiplication factor is one (MF = 0). The
PLL output frequency is twice the maximum system frequency. This double frequency is
needed to generate GCLK1 and GCLK2 clocks. On power-up, with a 4-MHz or 20-MHz
crystal and the default MF settings, VCOOUT will be 40 MHz and the system clock will
be 20 MHz.
8-4
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual MOTOROLA