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Two SCI messages can be separated with minimum idle time by using a preamble of 10
bit-times (11 if a 9-bit data format is specified) of marks (logic ones). Follow these steps:
1. Write the last data frame of the first message to the TDRx
2. Wait for TDRE to go high, indicating that the last data frame is transferred to the
transmit serial shifter
3. Clear TE and then set TE back to one. This queues the preamble to follow the stop
bit of the current transmission immediately.
4. Write the first data frame of the second message to register TDRx
In this sequence, if the first data frame of the second message is not transferred to TDRx
prior to the finish of the preamble transmission, then the transmit data line (TXDx pin)
marks idle (logic one) until TDRx is written. In addition, if the last data frame of the first
message finishes shifting out (including the stop bit) and TE is clear, TC goes high and
transmission is considered complete. The TXDx pin reverts to being a general-purpose
output pin.
15.7.7.6 Receiver Operation
The receiver can be divided into two segments. The first is the receiver bit processor logic
that synchronizes to the asynchronous receive data and evaluates the logic sense of each bit
in the serial stream. The second receiver segment controls the functional operation and the
interface to the CPU including the conversion of the serial data stream to parallel access by
the CPU.
15.7.7.7 Receiver Bit Processor
The receiver bit processor contains logic to synchronize the bit-time of the incoming data
and to evaluate the logic sense of each bit. To accomplish this an RT clock, which is 16
times the baud rate, is used to sample each bit. Each bit-time can thus be divided into 16
time periods called RT1–RT16. The receiver looks for a possible start bit by watching for
a high-to-low transition on the RXDx pin and by assigning the RT time labels appropriately.
When the receiver is enabled by writing RE in SCCxR1 to one, the receiver bit pro-cessor
logic begins an asynchronous search for a start bit. The goal of this search is to gain
synchronization with a frame. The bit-time synchronization is done at the beginning of each
frame so that small differences in the baud rate of the receiver and transmitter are not
cumulative. SCIx also synchronizes on all one-to-zero transitions in the serial data stream,
which makes SCIx tolerant to small frequency variations in the received data stream.
The sequence of events used by the receiver to find a start bit is listed below.
1. Sample RXDx input during each RT period and maintain these samples in a serial
pipeline that is three RT periods deep.
2. If RXDx is low during this RT period, go to step 1.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 15. Queued Serial Multi-Channel Module
Serial Communication Interface
15-59
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