Exception Model - Motorola MPC533 Reference Manual

Exception Model

These simple addressing modes allow efficient address generation for memory accesses.
Calculation of the effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length
exceeds the maximum effective address, the storage operand is considered to wrap around
from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned
binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
3.11 Exception Model
The MPC500 exception mechanism allows the processor to change to supervisor state as a
result of external signals, errors, or unusual conditions that arise in the execution of
instructions. When exceptions occur, information about the state of the processor is saved
to certain registers, and the processor begins execution at an address (exception vector)
predetermined for each exception. Processing of exceptions occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more
specific condition may be determined by examining a register associated with the exception
— for example, the DAE/source instruction service register (DSISR). Additionally, some
exception conditions can be explicitly enabled or disabled by software.
The MPC5xx architecture requires that exceptions be taken in program order; therefore,
although a particular implementation may recognize exception conditions out of order, they
are handled strictly in order with respect to the instruction stream. When an
instruction-caused exception is recognized, any unexecuted instructions that appear earlier
in the instruction stream, including any that have not yet entered the execute state, are
required to complete before the exception is taken. For example, if a single instruction
encounters multiple exception conditions, those exceptions are taken and handled
sequentially. Likewise, exceptions that are asynchronous and precise are recognized when
they occur, but are not handled until all instructions currently in the execute stage
successfully complete execution and report their results.
Note that exceptions can occur while an exception handler routine is executing, and
multiple exceptions can become nested. It is up to the exception handler to save the
appropriate machine state if it is desired that control be returned to the excepting program.
In many cases, after the exception handler handles an exception, there is an attempt to
execute the instruction that caused the exception. Instruction execution continues until the
next exception condition is encountered. This method of recognizing and handling
exception conditions sequentially guarantees that the machine state is recoverable and
processing can resume without losing instruction results.
3-38 MPC533 Reference Manual MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE