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Signal Name
BI / STS
Burst inhibit/
Transfer Start
BR
Bus request
BG
Bus grant
BB
Bus busy
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 9-1. MPC533 SIU Signals (continued)
Pins
Active
1
Low
Arbitration
1
Low
1
Low
1
Low
Chapter 9. External Bus Interface
Bus Interface Signal Descriptions
I/O
Burst Inhibit: Driven by the slave device to which the
I
current transaction was addressed. Indicates that the
current slave does not support burst mode.
Burst Inhibit: Driven by the MPC533 when the slave
device is controlled by the on-chip Memory Controller.
The MPC533 also asserts BI for any external master
burst access to internal MPC533 memory space.
O
Special Transfer Start: Driven by the MPC533 when it
owns the external bus. Indicates the start of a
transaction on the external bus or signals the
beginning of an internal transaction in show cycle
mode.
I
When the internal arbiter is enabled, BR assertion
indicates that an external master is requesting the bus.
O
Driven by the MPC533 when the internal arbiter is
disabled and the chip is not parked.
When the internal arbiter is enabled, the MPC533
asserts this signal to indicate that an external master
O
may assume ownership of the bus and begin a bus
transaction. The BG signal should be qualified by the
master requesting the bus in order to ensure it is the
bus owner:
Qualified bus grant = BG & ~ BB
When the internal arbiter is disabled, BG is sampled
I
and properly qualified by the MPC533 when an
external bus transaction is to be executed by the chip.
When the internal arbiter is enabled, the MPC533
asserts this signal to indicate that it is the current
owner of the bus.
O
When the internal arbiter is disabled, the MPC533
asserts this signal after the external arbiter has
granted the ownership of the bus to the chip and it is
ready to start the transaction.
When the internal arbiter is enabled, the MPC533
samples this signal to get indication of when the
I
external master ended its bus tenure (BB negated).
When the internal arbiter is disabled, the BB is
sampled to properly qualify the BG line when an
external bus transaction is to be executed by the chip.
Description
9-7
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