Motorola MPC533 Reference Manual page 211

Address
0x2F C10C
0x2F C110
0x2F C114
0x2F C118
0x2F C11C
0x2F C120–0x2F C13C Reserved
0x2F C140
0x2F C144
0x2F C148–0x2F C174 Reserved
1
0x2F C178
0x2F C17A–0x2F C1FC Reserved
0x2F C200
0x2F C204
0x2F C208
0x2F C20C–0x2F C21C Reserved
0x2F C220
0x2F C224
0x2F C228
0x2F C22C
0x2F C230–0x2F C23C Reserved
0x2F C240
MOTOROLA Chapter 5. Unified System Interface Unit (USIU) Overview
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 5-1. USIU Address Map (continued)
Option Register 1 (OR1)
See Table 10-11 for bit descriptions.
Base Register 2 (BR2)
See Table 10-9 for bit descriptions.
Option Register 2 (OR2)
See Table 10-11 for bit descriptions.
Base Register 3 (BR3)
See Table 10-9 for bit descriptions.
Option Register 3 (OR3)
See Table 10-11 for bit descriptions.
Dual-Mapping Base Register (DMBR)
See Table 10-12 for bit descriptions.
Dual-Mapping Option Register (DMOR)
See Table 10-13 for bit descriptions.
Memory Status (MSTAT)
See Table 10-8 for bit descriptions.
System Integration Timers
Time Base Status and Control (TBSCR)
See Table 6-18 for bit descriptions.
Time Base Reference 0 (TBREF0)
See Section 6.2.2.4.3, "Time Base Reference Registers (TBREF0 and TBREF1)," for bit
descriptions.
Time Base Reference 1 (TBREF1)
See Section 6.2.2.4.3, "Time Base Reference Registers (TBREF0 and TBREF1)," for bit
descriptions.
Real-Time Clock Status and Control (RTCSC)
See Table 6-19 for bit descriptions.
Real-Time Clock (RTC)
See Section 6.2.2.4.6, "Real-Time Clock Register (RTC)," for bit descriptions.
Real-Time Alarm Seconds (RTSEC) — Reserved
Real-Time Alarm (RTCAL)
See Section 6.2.2.4.7, "Real-Time Clock Alarm Register (RTCAL)," for bit descriptions.
PIT Status and Control (PISCR)
See Table 6-20 for bit descriptions.
Memory Map and Registers
Register
5-5