Motorola MPC533 Reference Manual page 537

written, reserved bits read zero and writes have no effect. They are typically written once
when the software initializes the QADC64E, and not changed afterwards.
MSB 1
0
Field IRL1
SRESET
Addr
Figure 14-5. QADC Interrupt Register (QADCINT)
Bits Name
0:4 IRL1 Queue 1 Interrupt Request Level — The IRL1 field establishes the queue 1 interrupt request level.
The 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. All interrupts
are presented on the IMB3. Interrupt level priority software determines which level has the highest
priority request.
5:9 IRL2 Queue 2 Interrupt Request Level — The IRL2 field establishes the queue 2 interrupt request level.
The 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. All interrupts
are presented on the IMB3. Interrupt level priority software determines which level has the highest
priority request.
10:15 — Reserved.
The QADC64E conditionally generates interrupts to the bus master via the IMB3 IRQ
signals. When the QADC64E sets a status bit assigned to generate an interrupt, the
QADC64E drives the IRQ bus. The value driven onto IRQ[7:0] represents the interrupt
level assigned to the interrupt source. Under the control of ILBS, each interrupt request
level is driven during the time multiplexed bus during one of four different time slots, with
eight levels communicated per time slot. No hardware priority is assigned to interrupts.
Furthermore, if more than one source on a module requests an interrupt at the same level,
the system software must assign a priority to each source requesting at that level.
Figure 14-6 displays the interrupt levels on IRQ with ILBS. Refer to Chapter 12, "U-Bus
to IMB3 Bus Interface (UIMB)" for more information.
IMB3 CLOCK
ILBS [1:0]
IMB3 IRQ [7:0]
MOTOROLAChapter 14. Queued Analog-to-Digital Converter Enhanced Mode Operation
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
0x30 4804 (QADCINT_A)
Table 14-5. QADCINT Bit Descriptions
00 01
10
IRQ IRQ
7:0 15:8
Figure 14-6. Interrupt Levels on IRQ with ILBS
Programming the QADC64E Registers
6 7 8 9
IRL2
0000_0000_0000_0000
Description
00 01
11
IRQ
IRQ
IRQ
31:24
23:16
10 11 12 13
—
10 11
7:0
14 LSB
15
14-13