Table of Contents
Advertisement
LOCK bit. Only then can the FLIP bit be changed. Finally, the LOCK bit must be cleared
again to protect the state of the FLIP bit from future writes.
1. Write LOCK = 1 to unlock operating mode bit.
2. Modify the value of FLIP as required.
— FLIP = 0 legacy mode enabled
— FLIP = 1 enhanced mode enabled
3. Write LOCK = 0 and new FLIP bit value to preserve the value of FLIP bit
• Example 1: switching from legacy mode to enhanced mode
— QADCMCR = 0x280; LOCK =1, SUPV = 1
— QADCMCR = 0x380; LOCK =1, write FLIP = 1, SUPV = 1
— QADCMCR = 0x180; LOCK = 0, FLIP = 1, SUPV = 1
Subsequent writes to the FLIP bit will have no effect while LOCK = 0.
• Example 2: switching from enhanced mode to legacy mode
— QADCMCR = 0x280 or 0x380; LOCK = 1, SUPV =1 (Can write FLIP = x since
value will not change)
— QADCMCR = 0x280; LOCK = 1, FLIP = 0, SUPV = 1
— QADCMCR = 0x080; LOCK = 0, FLIP = 0, SUPV =1
14.3.1.4 Supervisor/Unrestricted Address Space
The QADC64E memory map is divided into two segments: supervisor-only data space and
assignable data space. Access to supervisor-only data space is permitted only when the
software is operating in supervisor access mode. Assignable data space can be either
restricted to supervisor-only access or unrestricted to both supervisor and user data space
accesses. The SUPV bit in the QADCMCR designates the assignable space as supervisor
or unrestricted.
The following information applies to accesses to address space located within the module's
16-bit boundaries and where the response is a bus error. See Table 14-4 for more
information.
• Attempts to read a supervisor-only data space when not in the supervisor access
mode and SUPV = 1, causes the bus master to assert a bus error condition. No data
is returned. If SUPV = 0, the QADC64E asserts a bus error condition and no data is
returned.
• Attempts to write to supervisor-only data space when not in the supervisor access
mode and SUPV = 1, causes the bus master to assert a bus error condition. No data
is written. If SUPV = 0, the QADC64E asserts a bus error condition and the register
is not written.
MOTOROLAChapter 14. Queued Analog-to-Digital Converter Enhanced Mode Operation
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Programming the QADC64E Registers
14-11
Advertisement
Table of Contents
