Motorola MPC533 Reference Manual page 577

14.5.7 Configuration And Control Using the IMB3 Interface
The QADC64E module communicates with other microcontroller modules via the IMB3.
The QADC64E bus interface unit (BIU) coordinates IMB3 activity with internal
QADC64E bus activity. This section describes the operation of the BIU, IMB3 read/write
accesses to QADC64E memory locations, module configuration, and general-purpose I/O
operation.
14.5.7.1 QADC64E Bus Interface Unit
The BIU is designed to act as a slave device on the IMB3. The BIU has the following
functions: to respond with the appropriate bus cycle termination, and to supply IMB3
interface timing to all internal module signals.
BIU components consist of
• IMB3 buffers
• Address match and module select logic
• The BIU state machine
• Clock prescaler logic
• Data bus routing logic
• Interface to the internal module data bus
Normal accesses from the IMB3 to the QADC64E require two
clocks. However, if the CPU tries to access table locations
while the QADC64E is accessing them, the QADC64E
produces IMB3 wait states. From one to four IMB3 wait states
may be inserted by the QADC64E in the process of reading and
writing.
14.5.7.2 QADC64E Bus Accessing
The QADC64E supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses.
Coherency of results read (ensuring that all results read were taken consecutively in one
scan) is not guaranteed. For example, if a read of two consecutive 16-bit locations in a result
area is made, the QADC64E could change one 16-bit location in the result area between the
bus cycles. There is no holding register for the second 16-bit location. All read and write
accesses that require more than one 16-bit access to complete occur as two or more
independent bus cycles. Depending on bus master protocol, these accesses could include
misaligned and 32-bit accesses.
MOTOROLAChapter 14. Queued Analog-to-Digital Converter Enhanced Mode Operation
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
Digital Subsystem
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