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Key Features
4.1
Key Features
4.1.1
BIU Key Features
• Supports pipelined and burstable accesses to internal and external memories
• Supports the decoupled interface with the RCPU instruction unit
• Implements a parked master on the U-bus, resulting in zero clock delays for RCPU
fetch accesses to the U-bus
• Fully utilizes the U-bus pipeline for fetch accesses
• Avoids undesirable delays through a tight interface with the L2U module (fully
utilizing U-bus bandwidth and back-to-back accesses)
• Supports program trace and show cycles
• Supports a special attribute for debug port fetch accesses.
• Uses the RCPU mtspr/mfspr instructions to/from implementation-specific
special-purpose registers to perform programming
• Branch target buffer holds 8 entries for branch target addresses with FIFO
management.
4.1.2
IMPU Key Features
• There are four regions in which the base address and size can be programmed.
• Available region sizes include 2 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes,
128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16
Mbytes....4 Gbytes.
• Overlap between regions is allowed.
• Each of the four regions supports the following attributes:
— User/supervisor
— Guard attribute (causes an interrupt in case of speculative fetch attempt)
— Compressed/non-compressed (MPC534 only)
• Software enables or disables the IMPU.
• Global region entry declares the default access attributes for all memory areas not
covered by the four regions:
• The RCPU gets the instruction storage protection exception generated upon
— An access violation of protection attributes
— A fetch from a guarded region.
• The RCPU MSR[IR] bit controls IMPU protection.
• Programming is performed by using the RCPU mtspr/mfspr instructions to/from
implementation specific special-purpose registers.
4-2
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual
MOTOROLA
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