Motorola MPC533 Reference Manual page 131

FEX and VX are the logical ORs of other FPSCR bits. Therefore these two bits are not
listed among the FPSCR bits directly affected by the various instructions.
MSB 1 2
0
Field FX FEX VX
Reset
16 17 18
Field FPRF[1:4]
Reset
Figure 3-6. Floating-Point Status and Control Register (FPSCR)
A listing of FPSCR bit settings is shown in Table 3-5.
Bits Name
0 FX Floating-point exception summary. Every floating-point instruction implicitly
sets FPSCR[FX] if that instruction causes any of the floating-point exception
bits in the FPSCR to change from 0 to 1. The mcrfs instruction implicitly clears
FPSCR[FX] if the FPSCR field containing FPSCR[FX] has been copied. The
mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear FPSCR[FX]
explicitly.
1 FEX Floating-point enabled exception summary. This bit signals the occurrence of
any of the enabled exception conditions. It is the logical OR of all the
floating-point exception bits masked with their respective enable bits. The
mcrfs instruction implicitly clears FPSCR[FEX] if the result of the logical OR
described above becomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1
instructions cannot set or clear FPSCR[FEX] explicitly.
2 VX Floating-point invalid operation exception summary. This bit signals the
occurrence of any invalid operation exception. It is the logical OR of all of the
invalid operation exceptions. The mcrfs instruction implicitly clears
FPSCR[VX] if the result of the logical OR described above becomes zero. The
mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear FPSCR[VX]
explicitly.
3 OX Floating-point overflow exception.
4 UX Floating-point underflow exception.
5 ZX Floating-point zero divide exception.
6 XX Floating-point inexact exception.
7 VXSNAN Floating-point invalid operation exception for SNaN.
Floating-point invalid operation exception for ∞ - ∞.
8 VXISI
Floating-point invalid operation exception for ∞/∞.
9 VXIDI
10 VXZDZ Floating-point invalid operation exception for 0/0.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3 4 5 6
OX UX ZX XX VXSN
19 20 21 22
0 VX VX VXCVI
SOFT SQRT
Table 3-5. FPSCR Bit Descriptions
Chapter 3. Central Processing Unit
User Instruction Set Architecture (UISA) Register Set
7 8 9 10
VXISI VXIDI VXZDZ VXIMZ VXVC FR
AN
Unchanged
23 24 25 26
VE OE UE
Unchanged
Description
11 12 13 14
FI FPRF0
27 28 29 30 LSB
ZE XE NI RN
Sticky bit
Not sticky
Not sticky
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
3-15
15
31