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Development System Interface
21.3 Development System Interface
When debugging an existing system, it is sometimes desirable to be able to do so without
the need to insert any changes in the existing system. In some cases it is not desired, or even
impossible, to add load to the lines connected to the existing system. The development
system interface of the CPU supports such a configuration.
The development system interface of the CPU uses a dedicated serial port (the development
port) and, therefore, does not need any of the regular system interfaces. Controlling the
activity of the system from the development port is done when the CPU is in the debug
mode. The development port is a relatively economical interface (three pins) that allows the
development system to operate in a lower frequency than the frequency of the CPU. Note
that it is also possible to debug the CPU using monitor debugger software, for more
information refer to Section 21.5, "Software Monitor Debugger Support."
Debug mode is a state where the CPU fetches all instructions from the development port.
In addition, when in debug mode, data can be read from the development port and written
to the development port. This allows memory and registers to be read and modified by a
development tool (emulator) connected to the development port.
For protection purposes, two possible working modes are defined: debug mode enable and
debug mode disable. These working modes are selected only during reset. For more
information refer to Section 21.3.1.1, "Debug Mode Enable vs. Debug Mode Disable."
The user can work in debug mode starting from reset or the CPU can be programmed to
enter debug mode as a result of a predefined list of events. These events include all possible
interrupts and exceptions in the CPU system, including the internal breakpoints, together
with two levels of development port requests (masked and non-masked) and one peripheral
breakpoint request that can be generated by any one of the peripherals of the system
(including internal and external modules). Each event can be programmed either to be
treated as a regular interrupt that causes the machine to branch to its interrupt vector, or to
be treated as a special interrupt that causes debug mode entry.
When in debug mode an rfi instruction will return the machine to its regular work mode.
The relationship between the debug mode logic to the rest of the CPU chip is shown in
Figure 21-6.
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MPC533 Reference Manual
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