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does not allow other unrelated master accesses or bus arbitration to intervene between the
transfers. If any of the transactions except the first is re-tried during an access to a small
port, then a machine-check exception is generated to the RCPU.
CLKOUT
BR
BG
BB
ADDR[0:1]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
STS
1
Data
TA
1. For an illustration of device connections on the data bus, see Figure 9-23.
Figure 9-10. Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size
9.5.3
Data Bus Pre-Discharge Mode
Pre-discharge mode is provided for applications that use 3.3-V/5-V external memories
while the MPC533 data bus pads are optimized to 2.6-V memories, and cannot tolerate
more than 3.1 V. When connecting 3.3-V devices to the EBUS, and performing read and
write operations, this mode should be invoked in order to avoid long term reliability issues
of the data pads.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
ADDR
00
ABCDEFGH
Chapter 9. External Bus Interface
ADDR + 2
10
EFGHEFGH
Bus Operations
9-15
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