Motorola MPC533 Reference Manual page 715

Bits Name
0:4 — Reserved
5:7 IRL Interrupt request level. When the TouCAN generates an interrupt request, this field
determines which of the interrupt request signals is asserted.
8:9 ILBS Interrupt level byte select. This field selects one of four time-multiplexed slots during which
the interrupt request is asserted. The ILBS and IRL fields together select one of 32 effective
interrupt levels.
00 Levels 0 to7
01 Levels 8 to 15
10 Levels 16 to 23
11 Levels 24 to 31
10:15 — Reserved
16.7.4 Control Register 0 (CANCTRL0)
MSB
0
Field BOFFMSK ERRMSK
SRESET
Addr
Bits Name
0 BOFFMSK Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt.
0 Bus off interrupt disabled
1 Bus off interrupt enabled
1 ERRMSK Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt.
0 Error interrupt disabled
1 Error interrupt enabled
2:3 — Reserved
4:5 RXMODE Receive signal configuration control. These bits control the configuration of the CNRX0
signals. Refer to Table 16-14.
6:7 TXMODE Transmit signal configuration control. This bit field controls the configuration of the CNTX0
signals. Refer to Table 16-15.
8:15 CANCTRL1 See Table 16-16 and Section 16.7.5, "Control Register 1 (CANCTRL1)."
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 16-12. CANICR Bit Descriptions
1 2 3 4
— RXMODE
0x30 7486 (CANCTRL0_B)
Figure 16-11. Control Register 0 (CANCTRL0)
Table 16-13. CANCTRL0 Bit Descriptions
Chapter 16. CAN 2.0B Controller Module
Description
5 6 7
TXMODE
0000_0000_0000_0000
Description
Programmer's Model
8 9 10 11 12 13
CANCTRL1
14 LSB
15
16-29