Motorola MPC533 Reference Manual page 292

Clock Source Switching
When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low
state (provided that BUCS = 0).
8.5.3 Engineering Clock (ENGCLK)
ENGCLK is an output clock with a 50% duty cycle. Its frequency defaults to VCO/128,
which is 1/64 of the main system frequency. ENGCLK frequency can be programmed to
the main system frequency divided by a factor from one to 64, as controlled by the
ENGDIV[0:5] bits in the SCCR. ENGCLK can drive full- or half-strength, or it can also be
disabled (remaining in the high state). The drive strength is controlled by the EECLK[0:1]
bits in the SCCR. Disabling ENGCLK can reduce power consumption, noise, and
electromagnetic interference on the printed circuit board.
The full strength ENGCLK setting selects a 5-V driver, while
the half strength selection is a 2.6-V driver.
When the PLL is acquiring lock, the ENGCLK signal is disabled and remains in the low
state (provided that BUCS = 0).
Skew elimination between CLKOUT and ENGCLK is not
guaranteed.
8.6 Clock Source Switching
For limp mode support, clock source switching is supported. If for any reason the clock
source for the chip is not functioning, the option is to switch the system clock to the backup
clock ring oscillator, BUCLK.
This circuit consists of a loss-of-clock detector, which sets the LOCS status bit and LOCSS
sticky bit in the PLPRCR. If the LME bit in the SCCR is set, whenever LOCS is asserted,
the clock logic switches the system clock automatically to BUCLK and asserts hard reset
to the chip. Switching the system clock to BUCLK is also possible by software setting the
STBUC bit in SCCR. Switching from limp mode to normal system operation is
accomplished by clearing STBUC and LOCSS bits. This operation also asserts hard reset
to the chip.
At HRESET assertion, if the PLL output clock is not valid, the BUCLK will be selected
until software clears LOCSS bit in SCCR. At HRESET assertion, if the PLL output clock
is valid, the system will switch to oscillator/external clock. If during HRESET the PLL
loses lock or the clock frequency becomes slower than the required value, the system will
switch to the BUCLK. After HRESET negation the PLL lock condition does not effect the
system clock source selection.
8-14
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
NOTE
MPC533 Reference Manual MOTOROLA