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The event will be correctly detected as long as the compiler does not use a
load/store instruction with data size of byte.
• A partially supported scenario:
— Looking for:
Data size: half-word
Address: greater than or equal 0x00000002 and less than 0x0000000e
Data value: greater than 0x4e204e20 and less than 0x9c409c40
— Programming option:
One L-address comparator = 0x00000001 and program for greater than
One L-address comparator = 0x0000000e and program for less than
One L-data comparator = 0x4e204e20 and program for greater than
One L-data comparator = 0x9c409c40 and program for less than
Both byte masks = 0x0
Both L-data comparators program to half-word mode or to word mode
— Result:
The event will be correctly detected if the compiler chooses a load/store
instruction with data size of half-word. If the compiler chooses load/store
instructions with data size greater than half-word (word, multiple), there might
be some false detections.
These can be ignored only by the software that handles the breakpoints. The following
figure illustrates this partially supported scenario.
Possible false detect on these half-words when using word/multiple
Figure 21-3. Partially Supported Watchpoint/Breakpoint Example
21.2.1.4 Context Dependent Filter
The CPU can be programmed to either recognize internal breakpoints only when the
recoverable interrupt bit in the MSR is set (masked mode) or it can be programmed to
always recognize internal breakpoints (non-masked mode).
When the CPU is programmed to recognize internal breakpoints only when MSRRI = 1, it
is possible to debug all parts of the code except when the machine status save/restore
registers (SRR0 and SRR1), DAR (data address register) and DSISR (data storage interrupt
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
0x0000_0010
Chapter 21. Development Support
Watchpoints and Breakpoints Support
21-19
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