Table of Contents
Advertisement
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Data
Extra Clock Before Next Cycle Starts
(Read After Read From Different Banks, EHTR = 1)
Figure 10-18 shows two consecutive read cycles from the same bank. Even though
EHTR = 1, no extra clock cycle is inserted between the memory cycles. (In the case of two
consecutive read cycles to the same region, data contention is not a concern.)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Tdt
Figure 10-17. Consecutive Accesses
Chapter 10. Memory Controller
Chip-Select Timing
Long Tdt Allowed
10-21
Advertisement
Table of Contents
