Table of Contents
Advertisement
Clocks Unit Programming Model
MSB
1
0
Field DBCT
COM
PORESET
1
0
ID(2)
HRESET
U
0
ID(2)
16
17
EECLK[0:1]
PORESET
0
0
HRESET
Addr
1
The hard reset value is a reset configuration word value, extracted from the indicated internal data bus lines. Refer to
Section 7.5.2, "Hard Reset Configuration Word (RCW)."
2
EQ2 = MODCK1
3
EQ3 = (MODCK1 & MODCK2 & MODCK3) | (MODCK1 & MODCK2 & MODCK3) | (MODCK1 & MODCK2 & MODCK3). See
Table 8-1.
4
RTDIV will be 0 if MODCK[1:3] = 000.
Figure 8-13. System Clock and Reset Control Register (SCCR)
Bits
Name
0
DBCT
1:2
COM
8-30
2
3
4
DCSLR MFPDL LPML TBS RTDIV
1
0000
1
18
19
20
ENGDIV[0:5]
1
1
1
Unaffected
COM[1] bit default value is determined during by BDRV reset
configuration
bit;
Configuration Word (RCW).
Table 8-9. SCCR Bit Descriptions
Disable backup clock for timers. The DBCT bit controls the timers clock source while the
chip is in limp mode. If DBCT is set, the timers clock (TMBLCK, PITRCLK) source will not
be the backup clock, even if the system clock source is the backup clock ring oscillator. The
real-time clock source will be EXTAL or EXTCLK according to RTSEL bit (see description
in bit 11 below), and the time base clocks source will be determined according to TBS bit
and MODCK1.
0 If the chip is in limp mode, the timer clock source is the backup (limp) clock
1 The timer clock source is either the external clock or the crystal (depending on the current
clock mode selected)
Clock Output Mode – The COM and CQDS bits control the output buffer strength of the
CLKOUT and external bus pins. When both COM bits are set the CLKOUT pin is held in
the high (1) state and external bus pins are driven at reduced drive. These bits can be
dynamically changed without generating spikes on the CLKOUT and external bus pins. If
CLKOUT pin is not connected to external circuits, set both bits (disabling CLKOUT) to
minimize noise and power dissipation. The default value for COM[1] is determined by the
BDRV bit in the reset configuration word. See Table 7-5. For CLKOUT control see
Table 8-10.
MPC533 Reference Manual
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
6
7
8
4
STBUC CQDS PRQEN RTSEL BUCS EBDF[0:1] LME
1
1
Unaffected
21
22
23
24
—
1
1
1
0x2F C280
NOTE
See
Section 7.5.2,
Description
9
10
11
12
2
0
1
EQ2
1
Unaffected
25
26
27
28
DFNL[0:2]
—
0000_0000
0000_0000
"Hard
Reset
13
14
15
1
3
0
ID[13:14]
EQ3
1
ID[13:14]
U
29
30
LSB
31
DFNH[0:2]
MOTOROLA
Advertisement
Table of Contents
