Motorola MPC533 Reference Manual page 9

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Number
6.1.10 Software Watchdog Timer (SWT) ................................................................. 6-22
6.1.11 Freeze Operation............................................................................................ 6-24
6.1.12 Low Power Stop Operation............................................................................ 6-24
6.2 Memory Map and Register Definitions ............................................................. 6-24
6.2.1 Memory Map ................................................................................................. 6-25
6.2.2 System Configuration and Protection Registers ............................................ 6-25
6.2.2.1 System Configuration Registers ................................................................ 6-26
6.2.2.1.1
6.2.2.1.2
6.2.2.1.3
6.2.2.2 SIU Interrupt Controller Registers............................................................. 6-32
6.2.2.2.1
6.2.2.2.2
6.2.2.2.3
6.2.2.2.4
6.2.2.2.5
6.2.2.2.6
6.2.2.2.7
6.2.2.2.8
6.2.2.2.9
6.2.2.3 System Protection Registers ...................................................................... 6-39
6.2.2.3.1
6.2.2.3.2
6.2.2.3.3
6.2.2.4 System Timer Registers ............................................................................. 6-41
6.2.2.4.1
6.2.2.4.2
6.2.2.4.3
6.2.2.4.4
6.2.2.4.5
6.2.2.4.6
6.2.2.4.7
6.2.2.4.8
6.2.2.4.9
6.2.2.4.10
6.2.2.5 General-Purpose I/O Registers .................................................................. 6-47
6.2.2.5.1
6.2.2.5.2
6.2.2.5.3
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Contents
SIU Module Configuration Register (SIUMCR)................................... 6-26
Internal Memory Map Register (IMMR)............................................... 6-29
External Master Control Register (EMCR) ........................................... 6-30
SIU Interrupt Pending Register (SIPEND)............................................ 6-33
SIU Interrupt Pending Register 2 (SIPEND2)....................................... 6-33
SIU Interrupt Pending Register 3 (SIPEND3)....................................... 6-34
SIU Interrupt Mask Register (SIMASK)............................................... 6-34
SIU Interrupt Mask Register 2 (SIMASK2) ......................................... 6-35
SIU Interrupt Mask Register 3 (SIMASK3).......................................... 6-36
SIU Interrupt Edge Level Register (SIEL) ............................................ 6-36
SIU Interrupt Vector Register (SIVEC)................................................. 6-36
Interrupt In-Service Registers (SISR2 and SISR3) ............................... 6-38
System Protection Control Register (SYPCR) ...................................... 6-39
Software Service Register (SWSR)....................................................... 6-40
Transfer Error Status Register (TESR).................................................. 6-40
Decrementer Register (DEC)................................................................. 6-41
Time Base SPRs (TB)............................................................................ 6-42
Time Base Reference Registers (TBREF0 and TBREF1)..................... 6-42
Time Base Control and Status Register (TBSCR)................................. 6-43
Real-Time Clock Status and Control Register (RTCSC) ...................... 6-44
Real-Time Clock Register (RTC) .......................................................... 6-45
Real-Time Clock Alarm Register (RTCAL).......................................... 6-45
Periodic Interrupt Status and Control Register (PISCR) ....................... 6-45
Periodic Interrupt Timer Count Register (PITC)................................... 6-46
Periodic Interrupt Timer Register (PITR).............................................. 6-47
SGPIO Data Register 1 (SGPIODT1) .................................................. 6-47
SGPIO Data Register 2 (SGPIODT2) .................................................. 6-48
SGPIO Control Register (SGPIOCR) ................................................... 6-49
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