Motorola MPC533 Reference Manual page 630

Queued Serial Peripheral Interface
0x30 5140
or 0x30 5540
Receive
0x30 517F
or 0x30 557F
Half-Word
15.6.2.1 Receive RAM
Data received by the QSPI is stored in this segment, to be read by the CPU. Data stored in
the receive RAM is right-justified, (i.e., the least significant bit is always in the right-most
bit position within the word regardless of the serial transfer length). Unused bits in a receive
queue entry are set to zero by the QSPI upon completion of the individual queue entry. The
CPU can access the data using byte, half-word, or word addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU uses
this information to determine which locations in receive RAM contain valid data before
reading them.
15.6.2.2 Transmit RAM
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally
writes one word of data into this segment for each queue command to be executed. If the
corresponding peripheral, such as a serial input port, is used solely to input data, then this
segment does not need to be initialized.
Data must be written to transmit RAM in a right-justified format. The QSPI cannot modify
information in the transmit RAM. The QSPI copies the information to its data serializer for
transmission. Information remains in transmit RAM until overwritten.
15.6.2.3 Command RAM
Command RAM is used by the QSPI in master mode. The CPU writes one byte of control
information to this segment for each QSPI command to be executed. The QSPI cannot
modify information in command RAM.
Command RAM consists of 32 bytes. Each byte is divided into two fields. The peripheral
chip-select field, enables peripherals for transfer. The command control field provides
transfer options.
15-24
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
RR0 0x30 5180
RR1
or 0x30 5580
RR2
RAM
RRD
RRE
RRF
0x30 51BF
oe 0x30 55BF
Figure 15-16. QSPI RAM
MPC533 Reference Manual
TR0
0x30 51C0
TR1
or 0x30 55C0
TR2
Transmit
RAM
TRD
TRE
TRF
0x30 51DF
or 0x30 55DF
Half-Word
CR0
CR1
CR2
Command
RAM
CRD
CRE
CRF
Byte
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