Motorola MPC533 Reference Manual page 346

Bus Operations
9.5.6 Alignment and Packaging of Transfers
The MPC533 external bus requires natural address alignment:
• Byte accesses allow any address alignment
• Half-word accesses require address bit 31 to equal zero
• Word accesses require address bits 30 – 31 to equal zero
• Burst accesses require address bits 30 – 31 to equal zero
The MPC533 performs operand transfers through its 32-bit data port. If the transfer is
controlled by the internal memory controller, the MPC533 can support 8- and 16-bit data
port sizes.
The bus requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 32-bit port resides on DATA[0:31], a 16-bit port must reside on
DATA[0:15], and an 8-bit port must reside on DATA[0:7]. The MPC533 always tries to
transfer the maximum amount of data on all bus cycles. For a word operation, it always
assumes that the port is 32 bits wide when beginning the bus cycle.
InFigure 9-22, Figure 9-23 Table 9-2, and Table 9-3, the following conventions are used:
• OP0 is the most-significant byte of a word operand and OP3 is the least-significant
byte.
• The two bytes of a half-word operand are either OP0 (most-significant) and OP1 or
OP2 (most-significant) and OP3, depending on the address of the access.
• The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on
the address of the access.
0
OP0
OP0
OP0
Figure 9-23 illustrates the device connections on the data bus.
9-30
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
OP1
OP1
OP1
Figure 9-22. Internal Operand Representation
MPC533 Reference Manual
OP2 OP3
OP2 OP3
OP2
OP3
31
Word
Half-word
Byte
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