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3.7.3
Floating-Point Status and Control Register (FPSCR) ................................... 3-14
3.7.4
Condition Register (CR) ................................................................................ 3-17
3.7.4.1
Condition Register CR0 Field Definition .................................................. 3-18
3.7.4.2
Condition Register CR1 Field Definition .................................................. 3-18
3.7.4.3
Condition Register CRn Field - Compare Instruction ............................ 3-19
3.7.5
Integer Exception Register (XER)................................................................. 3-19
3.7.6
Link Register (LR)......................................................................................... 3-20
3.7.7
Count Register (CTR).................................................................................... 3-21
3.8
VEA Register Set - Time Base (TB) ............................................................... 3-21
3.9
OEA Register Set............................................................................................... 3-22
3.9.1
Machine State Register (MSR) ...................................................................... 3-22
3.9.2
DAE/Source Instruction Service Register (DSISR) ...................................... 3-24
3.9.3
Data Address Register (DAR) ....................................................................... 3-25
3.9.4
Time Base Facility (TB) - OEA .................................................................. 3-25
3.9.5
Decrementer Register (DEC)......................................................................... 3-26
3.9.6
Machine Status Save/Restore Register 0 (SRR0) .......................................... 3-26
3.9.7
Machine Status Save/Restore Register 1 (SRR1) .......................................... 3-27
3.9.8
General SPRs (SPRG0-SPRG3) ................................................................... 3-27
3.9.9
Processor Version Register (PVR)................................................................. 3-28
3.9.10
Implementation-Specific SPRs ...................................................................... 3-29
3.9.10.1
EIE, EID, and NRI Special-Purpose Registers.......................................... 3-29
3.9.10.2
Floating-Point Exception Cause Register (FPECR) .................................. 3-29
3.9.10.3
Additional Implementation-Specific Registers.......................................... 3-30
3.10
Instruction Set .................................................................................................... 3-30
3.10.1
Instruction Set Summary ............................................................................... 3-32
3.10.2
Recommended Simplified Mnemonics.......................................................... 3-37
3.10.3
Calculating Effective Addresses .................................................................... 3-37
3.11
Exception Model................................................................................................ 3-38
3.11.1
Exception Classes .......................................................................................... 3-39
3.11.2
Ordered Exceptions........................................................................................ 3-39
3.11.3
Unordered Exceptions.................................................................................... 3-39
3.11.4
Precise Exceptions ......................................................................................... 3-40
3.11.5
Exception Vector Table .................................................................................. 3-40
3.12
Instruction Timing.............................................................................................. 3-40
3.13
User Instruction Set Architecture (UISA) ......................................................... 3-42
3.13.1
Computation Modes....................................................................................... 3-42
3.13.2
Reserved Fields.............................................................................................. 3-42
3.13.3
Classes of Instructions ................................................................................... 3-43
3.13.4
Exceptions...................................................................................................... 3-43
3.13.5
Branch Processor ........................................................................................... 3-43
3.13.6
Instruction Fetching ....................................................................................... 3-43
MOTOROLA
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
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