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PCS_IN[3:0] is driven from QSMCM module. PCS_OUT[7:0]
will be driven from the pads to the pins. If the bits PCS4EN,
PCS5EN, PCS6EN, PCS7EN are negated (logic 0),
PCS_OUT[3:0] will be the same as PCS_IN[3:0]. The design
assumes that if one of these enable bits is set, PCS function is
selected in QSMCM module.
15.6.5.8 Master Wraparound Mode
Wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to
pointer address 0x0 or to the address pointed to by NEWQP, depending on the state of the
WRTO bit in SPCR2.
In wraparound mode, the QSPI cycles through the queue continuously, even while the QSPI
is requesting interrupt service. SPE is not cleared when the last command in the queue is
executed. New receive data overwrites previously received data in receive RAM. Each time
the end of the queue is reached, the SPIF flag is set. SPIF is not automatically reset. If
interrupt-driven QSPI service is used, the service routine must clear the SPIF bit to end the
current interrupt request. Additional interrupt requests during servicing can be prevented
by clearing SPIFIE, but SPIFIE is buffered. Clearing it does not end the current request.
Wraparound mode is exited by clearing the WREN bit or by setting the HALT bit in
SPCR3. Exiting wraparound mode by clearing SPE is not recommended, as clearing SPE
may abort a serial transfer in progress. The QSPI sets SPIF, clears SPE, and stops the first
time it reaches the end of the queue after WREN is cleared. After HALT is set, the QSPI
finishes the current transfer, then stops executing commands. After the QSPI stops, SPE can
be cleared.
15.6.6
Slave Mode
Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the QSPI is
unable to initiate serial transfers. Transfers are initiated by an external SPI bus master. Slave
mode is typically used on a multi-master SPI bus. Only one device can be bus master
(operate in master mode) at any given time.
Before QSPI operation is initiated, QSMCM register PQSPAR must be written to assign
necessary pins to the QSPI. The pins necessary for slave mode operation are MISO, MOSI,
SCK, and PCS0/SS. MISO is used for serial data output in slave mode, and MOSI is used
for serial data input. Either or both may be necessary, depending on the particular
application. SCK is the serial clock input in slave mode and must be assigned to the QSPI
for proper operation. Assertion of the active-low slave select signal SS initiates slave mode
operation.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
Chapter 15. Queued Serial Multi-Channel Module
Queued Serial Peripheral Interface
15-41
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