Motorola MPC533 Reference Manual page 792

MIOS14 Interrupts
MSB 1
0
Field FLG FLG
31 30
SRESET
Addr
Figure 17-37. Interrupt Status Register (MIOS14SR1)
Bits Name
0:4 FLG31:27
5:6 —
7:9 FLGL24:22 Flag Bit — MMCSM flag bit [24:22]
10:15 FLG21:16
17.12.4.2 Interrupt Enable Register (MIOS14ER1)
This register contains the interrupt enable bits for the submodules. Each bit corresponds to
a given submodule.
MSB 1
0
Field EN EN
31 30
SRESET
Addr
Figure 17-38. Interrupt Enable Register (MIOS14ER1)
Bits Name
0:4 EN31:27 Enable Bits — MDASM enable bits [31:27]
5:6 — Reserved
7:9 EN24:22 Enable Bits — MMCSM enable bits [24:22]
10:15 EN21:16 Enable Bits — PWMSM enable bits [21:16]
17.12.4.3 Interrupt Request Pending Register (MIOS14RPR1)
This register is a read only register that contains the interrupt pending bits for the
submodules. Each bit corresponds to a given submodule. When one of these bits is set, it
means that a submodule raised its flag and the corresponding enable was set.
17-68
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
FLG FLG FLG —
29 28 27
Table 17-39. MIOS14SR1 Bit Descriptions
Flag Bits — MDASM flag bits [31:27]
Reserved
Flag Bits — PWMSM flag bits [21:16]
2 3 4 5
EN EN EN —
29 28 27
Table 17-40. MIOS14ER1 Bit Descriptions
MPC533 Reference Manual
6 7 8 9 10
FLG FLG FLG FLG
24 23 22 21
Undefined
0x30 6C40
Description
6 7 8 9 10
EN EN EN EN
24 23 22 21
Undefined
0x30 6C44
Description
11 12 13 14
FLG FLG FLG FLG
20 19 18 17
11 12 13 14
EN EN EN EN
20 19 18 17
MOTOROLA
LSB
15
FLG
16
LSB
15
EN
16