Motorola MPC533 Reference Manual page 385

CLKOUT
BR
BG
BB
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST
TS
BDIP
Data
TA
1
Figure 10-5. A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
ADDR[28:31] = 0b0000
00
Normal
Late
2 3 4 5
1st Data
Is Valid
Chapter 10. Memory Controller
Memory Controller Architecture
Expects Another Data
6 7 8
2nd Data 3rd Data
Is Valid Is Valid
Last Beat
No Data
Expected
9 10
4th Data
Is Valid
10-9