Motorola MPC533 Reference Manual page 645

conversion. Writing a value to the DTL field in SPCR1 specifies a delay period. The DT bit
in each command RAM byte determines whether the standard delay period (DT = 0) or the
specified delay period (DT = 1) is used. The following expression is used to calculate the
delay:
where DTL is in the range from one to 255.
A zero value for DTL causes a delay-after-transfer value of 8192 ÷ IMB3 clock frequency
(204.8 µs with a 40-MHz IMB3 clock).
If DT is zero in a command RAM byte, a standard delay is inserted.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also
be inserted between consecutive transfers to allow serial A/D converters to complete
conversion.
Adequate delay between transfers must be specified for long data streams because the QSPI
requires time to load a transmit RAM entry for transfer. Receiving devices need at least the
standard delay between successive transfers. If the IMB3 clock is operating at a slower rate,
the delay between transfers must be increased proportionately.
15.6.5.5 Transfer Length
There are two transfer length options. The user can choose a default value of eight bits, or
a programmed value from eight (0b1000) to 16 (0b0000) bits, inclusive. Reserved values
(from 0b0001 to 0b0111) default to eight bits. The programmed value must be written into
the BITS field in SPCR0. The BITSE bit in each command RAM byte determines whether
the default value (BITSE = 0) or the BITS value (BITSE = 1) is used.
15.6.5.6 Peripheral Chip Selects
Peripheral chip-select signals are used to select an external device for serial data transfer.
Chip-select signals are asserted when a command in the queue is executed. Signals are
asserted at a logic level corresponding to the value of the PCS[3:0] bits in each command
byte. More than one chip-select signal can be asserted at a time, and more than one external
device can be connected to the PCS pins, provided proper fanout is observed. PCS0 shares
a pin with the slave select SS signal, which initiates slave mode serial transfer. If SS is taken
low when the QSPI is in master mode, a mode fault occurs.
To configure a peripheral chip select, set the appropriate bit in the PQSPAR, then configure
the chip-select pin as an output by setting the appropriate bit in DDRQS. The value of the
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Delay after Transfer
Standard Delay after Transfer
Chapter 15. Queued Serial Multi-Channel Module
Queued Serial Peripheral Interface
32xDTL
= -------------------- -
f SYS
17
= -------------
f SYS
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