Motorola MPC533 Reference Manual page 623

A dedicated 160-byte RAM is used to store received data, data to be transmitted, and a
queue of commands. The CPU can access these locations directly. This allows serial
peripherals to be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 32 serial transfers without CPU
intervention. Each queue entry contains all the information needed by the QSPI to
independently complete one serial transfer.
A pointer identifies the queue location containing the data and command for the next serial
transfer. Normally, the pointer address is incremented after each serial transfer, but the CPU
can change the pointer value at any time. Support for multiple-tasks can be provided by
segmenting the queue.
The QSPI has four peripheral chip-select pins. The chip-select signals simplify interfacing
by reducing CPU intervention. If the chip-select signals are externally decoded, 16
independent select signals can be generated.
Wrap-around mode allows continuous execution of queued commands. In wraparound
mode, newly received data replaces previously received data in the receive RAM.
Wrap-around mode can simplify the interface with A/D converters by continuously
updating conversion values stored in the RAM.
Continuous transfer mode allows transfer of an uninterrupted bit stream. From eight to 512
bits can be transferred without CPU intervention. Longer transfers are possible, but
minimal intervention is required to prevent loss of data. A standard delay of 17 IMB3
clocks (0.8 µs with a 40-MHz IMB3 clock) is inserted between the transfer of each queue
entry.
15.6.1 QSPI Registers
The QSPI memory map, shown in Table 15-12, includes the QSMCM global and pin
control registers, four QSPI control registers (SPCR[0:3]), the status register (SPSR), and
the QSPI RAM. Registers and RAM can be read and written by the CPU. The memory map
can be divided into supervisor-only data space and assignable data space. The address
offsets shown are from the base address of the QSMCM module. Refer to Figure 4-3 for a
diagram of the MPC533 internal memory map.
1
Access
Address
S/U 0x30 5018
S/U 0x30 501A
S/U 0x30 501C
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 15-12. QSPI Register Map
2
MSB
See Table 15-13 for bit descriptions.
See Table 15-15 for bit descriptions.
See Table 15-16 for bit descriptions.
Chapter 15. Queued Serial Multi-Channel Module
Queued Serial Peripheral Interface
QSPI Control Register 0 (SPCR0)
QSPI Control Register 1 (SPCR1)
QSPI Control Register 2 (SPCR2)
LSB
15-17