Motorola MPC533 Reference Manual page 247

Table 6-14. SIU Interrupt Controller – Bit Acronym Definitions
Name
IRQn
LVLn
IMBIRQn
IRMn
LVMn
EDn
WMn
6.2.2.2.1 SIU Interrupt Pending Register (SIPEND)
MSB 1
0
Field IRQ0 LVL0 IRQ1 LVL1 IRQ2 LVL2 IRQ3 LVL3 IRQ4 LVL4 IRQ5 LVL5 IRQ6 LVL6 IRQ7 LVL7
SRESET
16 17
Field
SRESET
Addr
6.2.2.2.2 SIU Interrupt Pending Register 2 (SIPEND2)
MSB 1
0
Field IRQ0 LVL0
SRESET
16 17
Field IMB IMB
IRQ10 IRQ11
SRESET
Addr
Figure 6-16. SIU Interrupt Pending Register 2 (SIPEND2)
MOTOROLA
Intermodule Bus Interrupt Level n Request
2 3 4 5
18 19 20 21
Figure 6-15. SIU Interrupt Pending Register (SIPEND)
2 3 4 5
IMB IMB IMB IMB
IRQ0 IRQ1 IRQ2 IRQ3
18 19 20 21
IRQ3 LVL3 IMB IMB
IRQ12 IRQ13
Chapter 6. System Configuration and Protection
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Memory Map and Register Definitions
Description
Interrupt Signal n Request
Interrupt Level n Request
Interrupt Signal n Mask
Interrupt Level n Mask
Falling Edge Detect, Interrupt Signal n
Wakeup Mask, Interrupt Signal n
6 7 8
0000_0000_0000_0000
22 23 24
—
0000_0000_0000_0000
0x2F C010
6 7 8
IRQ1 LVL1 IMB
IRQ4 IRQ5
0000_0000_0000_0000
22 23 24
IMB IMB IRQ4 LVL4
IRQ14 IRQ15
0000_0000_0000_0000
0x2F C040
9 10 11 12
25 26 27 28
9 10 11 12
IMB IMB IMB IRQ2
IRQ6 IRQ7
25 26 27 28
IMB IMB IMB
IRQ16 IRQ17 IRQ18
13 14 15
29 30 LSB
31
13 14 15
LVL2 IMB IMB
IRQ8 IRQ9
29 30 LSB
31
IMB IRQ5 LVL5
IRQ19
6-33