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Interrupt Operation
The IRQMUX bits determine how many levels of IMB interrupts are sampled. Refer to
Table 12-4.
.
IRQMUX[0:1]
00
00, 00, 00.....
01
00, 01, 00, 01....
10
00, 01, 10, 00, 01, 10,.....
11
00, 01, 10, 11, 00, 01, 10, 11,....
12.4.4
Interrupt Synchronizer
The interrupt synchronizer latches the 32 levels of interrupts from the IMB bus into a
register which can be read by the CPU or other U-bus master. Since there are only eight
lines for interrupts on the IMB and 32 levels of interrupts are possible, the 32 interrupt
levels are multiplexed onto eight IMB interrupt lines. Apart from latching these interrupts
in the register (UIPEND register), the interrupt synchronizer drives the interrupts onto the
U-bus, where they are latched by the interrupt controller in the USIU.
If IMB modules drive interrupts on any of the 24 levels (levels eight through 31), they will
be latched in the interrupt pending register (UIPEND) in the UIMB. If any of the register
bits 7 to 31 are set, then bit 7 will be set as well. Software must poll this register to find out
which of the levels 7 to 31 are asserted.
The UIPEND register contains a status bit for each of the 32 interrupt levels. Each bit of the
register is a read-only status bit, reflecting the current state of the corresponding interrupt
signal. For each of the 32 interrupt levels, a corresponding bit of the UIPEND register is set.
Figure 12-4 shows how the eight interrupt lines are connected to the UIPEND register to
represent 32 levels of interrupts. Figure 12-6 shows the implementation of the interrupt
synchronizer.
12-6
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 12-4. IRQMUX Functionality
ILBS sequence
MPC533 Reference Manual
Description
Latch 0:7 IMB interrupt levels
Latch 0:15 IMB interrupt levels
Latch 0:23 IMB interrupt levels
Latch 0:31 IMB interrupt levels
MOTOROLA
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