Motorola MPC533 Reference Manual page 379

start (MTS) strobe permits one master on a bus to access external memory through the chip
selects on another.
The memory controller functionality allows MPC533-based systems to be built with little
or no glue logic. A minimal system using no glue logic is shown in Figure 10-3. In this
example CS[0] is used for a 16-bit boot EPROM and CS[1] is used for a 32-bit SRAM. The
WE/BE[0:3] signals are used both to program the EPROM and to enable write access to
various bytes in the RAM.
Address
MPC5xx
WE/BE[0:3]
Figure 10-3. MPC533 Simple System Configuration
10.2 Memory Controller Architecture
The memory controller consists of a basic machine that handles the memory access cycle:
the general-purpose chip-select machine (GPCM).
When any of the internal masters request a new access to external memory, the address of
the transfer (with 17 bits having a mask) and the address type (with three bits having a
mask) are compared to each one of the valid banks defined in the memory controller. Refer
to Figure 10-4.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
CS[0]
OE
Data
CS[1]
Chapter 10. Memory Controller
Memory Controller Architecture
Address
CE
OE
WE/BE[0:1]
DATA[0:15]
[0:15]
EPROM
Address
CE
WE/BE[0:3]
Data
[0:31]
OE
SRAM
10-3