Motorola MPC533 Reference Manual page 253

6.2.2.3 System Protection Registers
6.2.2.3.1 System Protection Control Register (SYPCR)
The system protection control register (SYPCR) controls the system monitors, the software
watchdog period, and the bus monitor timing. This register can be read at any time, but can
be written only once after system reset.
MSB 1
0
Field
HRESET
16 17 18
Field
HRESET
Addr
Figure 6-26. System Protection Control Register (SYPCR)
Bits Name
0:15 SWTC Software watchdog timer count. This field contains the count value of the software watchdog
timer.
16:23 BMT Bus monitor timing. This field specifies the time-out period, in eight-system-clock resolution, of
the bus monitor. BMT must be set to non zero even if the bus monitor is not enabled.
24 BME Bus monitor enable
0 Disable bus monitor
1 Enable bus monitor
25:27 — Reserved
28 SWF Software watchdog freeze
0 Software watchdog continues to run while FREEZE is asserted
1 Software watchdog stops while FREEZE is asserted
29 SWE Software watchdog enable. Software should clear this bit after a system reset to disable the
software watchdog timer.
0 Watchdog is disabled
1 Watchdog is enabled
30 SWRI Software watchdog reset/interrupt select
0 Software watchdog time-out causes a non-maskable interrupt to the RCPU
1 Software watchdog time-out causes a system reset
31 SWP Software watchdog prescale
0 Software watchdog timer is not prescaled
1 Software watchdog timer is prescaled by 2048
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5 6
19 20 21 22
BMT
1111_1111
Table 6-15. SYPCR Bit Descriptions
Chapter 6. System Configuration and Protection
Memory Map and Register Definitions
7 8 9 10
SWTC
1111_1111_1111_1111
23 24 25 26
BME —
0 000
0x2F C004
Description
11 12 13 14
27 28 29 30
SWF SWE SWRI SWP
0 1 1
15
LSB
31
1
6-39