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Complete transmit and receive cycles are based on the PPM_TSYNC clock. A cycle begins
on the rising edge of PPM_TSYNC, which goes high for one PPM_TCLK cycle. The
transmit signals, PPM_TX[0:1], will stay high as long as PPM_TSYNC is high (equal to
"1" in Figure 18-6). Data bits start to transmit on the falling edge of PPM_TSYNC. In
receive mode, valid data starts to shift into RX_SHIFTER on the falling edge of
PPM_TSYNC. PPM_TSYNC stays low until the contents of TX_DATA have been shifted
out and/or 16 bits have been shifted into RX_SHIFTER. One data bit is transferred every
PPM_TCLK cycle.
SYSCLK
PPM_TCLK
PPM_TSYNC
"1"
PPM_TX
PPM_RX
Shading of PPM_RX signifies value is unknown
Figure 18-6. One Transmit and Receive Cycle in SPI Mode
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
CH[0]
CH[1]
CH[2]
CH[0]
CH[1]
CH[2]
Chapter 18. Peripheral Pin Multiplexing (PPM) Module
One Cycle
CH[3]
CH[3]
Functional Description
CH[K]
"1"
CH[0]
CH[K]
CH[0]
18-7
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