Branch Prediction; Fixed-Point Processor; Fixed-Point Instructions - Motorola MPC533 Reference Manual

User Instruction Set Architecture (UISA)
instructions, the target address of the branch is the new value of the CTR. Condition is
evaluated correctly, including the value of the counter after decrement.

3.13.7.2 Branch Prediction

The core uses the y bit to predict path for pre-fetch. Prediction is only done for not-ready
branch conditions. No prediction is done for branches to the link or count register if the
target address is not ready. Refer to the RCPU Reference Manual (conditional branch
control) for more information.
3.13.8

Fixed-Point Processor

3.13.8.1 Fixed-Point Instructions

The core implements the following instructions:
• Fixed-point arithmetic instructions
• Fixed-point compare instructions
• Fixed-point trap instructions
• Fixed-point logical instructions
• Fixed-point rotate and shift instructions
• Move to/from system register instructions
All instructions are defined for the fixed-point processor in the UISA in the hardware. For
performance of the various instructions, refer to Table 3-22.
— Move To/From System Register Instructions. Move to/from invalid special
registers in which SPR0 = 1 yields invocation of the privilege instruction error
interrupt handler if the processor is in problem state. For a list of all implemented
special registers, refer to Table 3-2, and Table 3-3.
— Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of the
divisions in the divw[o][.] instruction (0x80000000
the contents of RT are 0x80000000; if Rc =1, the contents of bits in CR field 0
are LT = 1, GT = 0, EQ = 0, and SO is set to the correct value. If an attempt is
made to perform any of the divisions in the divw[o][.] instruction, <anything>
0. In cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable for 64-bit
implementations. In 32-bit implementations, if L = 1 the instruction form is
invalid. The core ignores this bit and therefore, the behavior when L = 1 is
identical to the valid form instruction with L = 0
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual
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-1, <anything> 0), then
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