Motorola MPC533 Reference Manual page 705

16.5.1 Debug Mode
Debug mode is entered when the FRZ1 bit in CANMCR is set and one of the following
events occurs:
• The HALT bit in the CANMCR is set; or
• The IMB3 FREEZE line is asserted
Once entry into debug mode is requested, the TouCAN waits until an intermission or idle
condition exists on the CAN bus, or until the TouCAN enters the error passive or bus off
state. Once one of these conditions exists, the TouCAN waits for the completion of all
internal activity. Once this happens, the following events occur:
• The TouCAN stops transmitting or receiving frames
• The prescaler is disabled, thus halting all CAN bus communication
• The TouCAN ignores its Rx signals and drives its Tx signals as recessive
• The TouCAN loses synchronization with the CAN bus and the NOTRDY and
FRZACK bits in CANMCR are set
• The CPU is allowed to read and write the error counter registers
After engaging one of the mechanisms to place the TouCAN in debug mode, the FRZACK
bit must be set before accessing any other registers in the TouCAN; otherwise unpredictable
operation may occur.
To exit debug mode, the IMB3 FREEZE line must be negated or the HALT bit in CANMCR
must be cleared.
Once debug mode is exited, the TouCAN resynchronizes with the CAN bus by waiting for
11 consecutive recessive bits before beginning to participate in CAN bus communication.
16.5.2 Low-Power Stop Mode
Before entering low-power stop mode, the TouCAN waits for the CAN bus to be in an idle
state, or for the third bit of intermission to be recessive. The TouCAN then waits for the
completion of all internal activity (except in the CAN bus interface) to be complete. Then
the following events occur:
• The TouCAN shuts down its clocks, stopping most internal circuits, thus achieving
maximum power savings
• The bus interface unit continues to operate, allowing the CPU to access the module
configuration register
• The TouCAN ignores its Rx signals and drives its Tx signals as recessive
• The TouCAN loses synchronization with the CAN bus, and the STOPACK and
NOTRDY bits in the module configuration register are set
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 16. CAN 2.0B Controller Module
Special Operating Modes
16-19