Motorola MPC533 Reference Manual page 778

MIOS14 Pulse Width Modulation Submodule (MPWMSM)
end of the next period; during this period the previous values are used for the period and
width This feature enables updates of the period and pulse-width values without getting
erroneous pulses.
17.10.4 Modular Input/Output Bus (MIOS14) Interface
The MPWMSM is connected to all the signals in the read/write and control bus, to allow
data transfer from and to the MPWMSM registers, and to control the MPWMSM in the
different possible situations.
• The MPWMSM is not using any of the 16-bit counter buses.
• The MPWMSM uses the request bus to transmit to the request submodule.
17.10.5 Effect of RESET on MPWMSM
The MPWMSM is affected by reset according to what is described in the section related to
register description.
The MPWMPERR, MPWMPULR, and MPWMCNTR registers, together with the clock
prescaler register bits, must be initialized by software, since they are undefined after
hardware reset.
A value must be written to the MPWMCNTR (which writes the same value into the
MPWMPERR) and a pulse width value written to MPWMPULR, before the MPWMSCR
is written to. The latter access initializes the clock prescaler.
17.10.6 MPWMSM Registers
The privilege level to access to the MPWMSM registers depends on the MIOS14MCR
SUPV bit. The privilege level is unrestricted after reset and can be change to supervisor by
software.
17.10.6.1 MPWMSM Registers Organization
The MPWMSM register map comprises four 16-bit register locations, as shown in
Table 17-26. All unused bits return zero when read by the software. All register addresses
in this section are specified as offsets from the base address of the MPWMSM.
Address
0x30 6000 MPWMSM0 Period Register (MPWMPERR)
17-54
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 17-26. MPWMSM Address Map
MPWMSM0
See Table 17-27 for bit descriptions.
MPC533 Reference Manual
Register
MOTOROLA