Motorola MPC533 Reference Manual page 417

Chapter 11
L-Bus to U-Bus Interface (L2U)
The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus
(L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection
unit (DMPU), which provides protection for data memory accesses.
The L2U is bidirectional. It allows load/store accesses not intended for the L-bus data RAM
to go to the U-bus. It also allows code execution from the L-bus data RAM and read/write
accesses from the U-bus to the L-bus.
The L2U directs bus traffic between the L-bus and the U-bus. When transactions start
concurrently on both buses, the L2U interface arbitrates to select which transaction is
handled. The top priority is assigned to U-bus to L-bus accesses; lower priority is assigned
to the load/store accesses by the RCPU.
11.1 General Features
• Non-pipelined master and slave on U-bus
— Does not start two back-to-back accesses on the U-bus
— Supports the U-bus pipelining by starting a cycle on the U-bus when U-bus pipe
depth is zero or one
— Does not accept back-to-back accesses from the U-bus master
• Non-pipelined master and slave on the L-bus
• Generates module selects for L-bus memory-mapped resources within a
programmable, contiguous block of storage
• Programmable data memory protection unit (DMPU)
• L-bus and U-bus snoop logic for the reservation protocol implemented by the
PowerPC compatible architecture
• L2U does not support dual mapping of L-bus or IMB3 space
• Show cycles for RCPU accesses to the CALRAM (none, all, writes)
— Protection for CALRAM accesses from the U-bus side (all accesses to the
CALRAM from the U-bus side are blocked once the CALRAM protection bit is
set)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 11. L-Bus to U-Bus Interface (L2U) 11-1