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attributes. Only CPU writes to this register will be transmitted. This register is not
accessible via the auxiliary port download request message.
This is the only READI register that is reset by HRESET.
MSB
1
0
Field
HRESET
16
17
18
Field
HRESET
Addr
Figure 22-2. READI Ownership Trace Register (OTR)
Bits
Name
0:31
CTP
READI ownership trace register, write only.
22.1.1.2 Tool-Mapped Registers
Table 22-5 defines READI registers that are not memory mapped and can only be accessed
through the development tool. Their corresponding access opcodes are also defined.
.
Access Opcode
8 (0x08)
10 (0x0A)
11(0x0B)
13 (0x0D)
15 (0x0F)
16 (0x10)
20 (0x14)
21 (0x15)
1
Not available on all revisions. Refer to the device errata for the version of silicon in use.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2
3
4
5
Current Task Process (CTP)
19
20
21
Current Task Process (CTP)
Table 22-4. OTR Bit Descriptions
Table 22-5. Tool-Mapped Register Space
Device ID Register (DID)
Development Control Register (DC)
Mode Control Register (MC)
User Base Address Register (UBA)
Read/Write Access Register (RWA)
Upload/Download Information Register (UDI)
Data Trace Attributes Register 1 (DTA1)
Data Trace Attributes Register 2 (DTA2)
Chapter 22. READI Module
NOTE
6
7
8
9
0000_0000_0000_0000
22
23
24
25
0000_0000_0000_0000
0x38 002C
Description
Register
1
Programming Model
10
11
12
13
26
27
28
29
Access Type
Read Only
Read Only
1
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
14
15
30
LSB
31
22-9
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